UPD16654 查看數據表（PDF） - NEC => Renesas Technology

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UPD16654

150/154 OUTPUT TFT-LCD GATE DRIVE

NEC => Renesas Technology 

µPD16654

Caution 2. Inserting bypass capacitor

Because the internal logic operates at a high voltage (VDD2-VEE1), insert a bypass capacitor of

about 0.1 µF between the respective power pins as shown below to secure the noise margin

of VIH and VIL.

VDD2

VCC

VSS

VEE2

0.1 µF

0.1 µF

0.1 µF

0.1 µF

VEE1

Do not input a switching signal to the Osel pin that selects the number of outputs. Connect this pin to VCC or VSS (VEE1).

5

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