UPD16879GS-BGG 查看數據表（PDF） - NEC => Renesas Technology

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UPD16879GS-BGG

MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT

NEC => Renesas Technology 

RESET

VD

VD

LATCH

Initialization

S1

S2

S3

S4 pulse 0

S5 PS

S6 PS

S7 release PS S8

S9 Enable S10 release PS S11

S12 data error S13 normal data S14

DATA

SCLK

OSCOUT

Start point wait

(FF1)

Start point wait+

Start point magnetize wait

(FF2)

ENABLE OUTNote 1

CHOPPING

EXP 0, 1

PULSE OUT

PULSE GATE

(FF3)

PULSE CHECKNote 2

(FF7)

CHECK SUMNote 3

S1

S2

S3

S4

S2

S3

S4

S4

S7

H level fixation

S8

It reverts from the VD

start after a PS release.

S8

L level fixation

S9

S9

S10

S10

S11

S11

S12

S12

S13

S13

S14

L level fixation

Start from

Stop from LATCH ↓

LATCH ↓

EXP can be change in PS period too.

S2

S3

S4

Pulse is nothing

because pulse

data is "0"

S5 to S7

Pulse is nothing

because PS data

Pulse count is done

in enable period too

S8

S9

S10

S11

Pulse is nothing

because

error data.

S13

Output L level

because

error data

SCLK

SDATA

1st byte → 13th byte

D0

D1

D2

D3

D4

D5

D6 D7

(LSB)

Data is held at rising edge SCLK

Notes 1. ENABLE is set at the falling edge of FF1 when the level changes from

low to high, and at the falling edge of FF2 when the level changes from

high to low.

2. FF7 is an output signal that is used to check for the presence or

absence of a pulse in the serial data, is updated at the falling edge of

LATCH and reset once at the rising edge of LATCH. If CHECK SUM

is other than "00h", FF7 goes low, inhibiting pulse output, even if a

pulse is generated.

3. CHECK SUM output is updated at the falling edge of LATCH.

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