UPD16879GS-BGG 查看數據表（PDF） - NEC => Renesas Technology

零件编号

产品描述 (功能)

生产厂家

UPD16879GS-BGG

MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT

NEC => Renesas Technology 

µPD16879

ELECTRICAL CHARACTERISTICS

(Unless otherwise specified, TA = 25°C, VDD = 3 V, VM = 5.4 V, fCLK = 4.5 MHz, COSC = 68 pF, CFIL = 1000 pF,

VREF = 250 mV, EVR = 100 mV (10000))

Parameter

Symbol

Conditions

MIN. TYP. MAX. Unit

Off state VM pin current

IMO(RESET) No load, Reset period

1.0

µA

Operating state VDD pin current

IDD

VDD pin current

IDD(RESET)

Power save state VDD pin current IDD(PS)1

IDD(PS)2

Output open

Reset period

tCLK = off

fCLK = 4.5 MHZ

3.0

mA

100

µA

100

µA

300

µA

High level input voltage

Low level input voltage

VIH

LATCH, SCLK, SDATA, VD, VD

VIL

RESET, OSCIN, VREFsel

0.7 × VDD

V

0.3 × VDD V

Input hysteresis vosltage

VH

0.3

V

Monitor output voltage 1

(EXTOUT α, β)

VOMα(H)

VOMβ(H)

VOMα(L)

VOMβ(L)

Monitor output voltage 2

(EXP 0,1 open drain)

VOEXP(H)

VOEXP(L)

High level input current

IIH

Low level input current

IIL

Reset pin high level input current IIH(RST)

Reset pin low level input current IIL(RST)

4th byte

Pull up (VDD)

IOEXP = 100 µA

VIN = VDD

VIN = 0

VRST = VDD

VRST = 0

0.9 × VDD

−0.3

0.9 × VDD

−1.0

−1.0

V

0.1 × VDD V

V

0.1 × VDD V

1.0

µA

µA

1.0

µA

µA

H bridge ON resistance

Chopping frequencyNote 1

RON

IM = 100 mA, upper + lower

fOSC

6.0

Ω

Refer to table 1 (TYP.)

kHz

Internal reference voltage

VD delay timeNote 2

VREF

∆tVD

225

250

275

mV

250

ns

Sin wave peak output current

(reference value)Note 3

FIL pin voltageNote 4

FIL pin step voltageNote 4

H bridge turn on timeNote 5

H bridge turn off timeNote 5

IM

VEVR

VEVRSTEP

tONH

tOFFH

L = 15 mH/R = 70 Ω ( 1 kHz)

RS = 6.8 Ω, fOSC = 72.58 kHz

EVR = 220 mV (11100)

EVR = 200 mV (11010)

VREF = 250 mV external input

Minimum step

IM = 100 mA

53

mA

370

400

430

mV

20

mV

2.0

µs

2.0

µs

Notes 1. When data are less than 7 (000111), PWM chopping doesn’t do it, and output pulse doesn’t occur.

When data are beyong 49, PWM chopping frequency becomes a 225 kHz fixation.

2. By OSCIN and VD sync circuit

3. FB pin is monitored.

4. FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin.

5. 10% to 90% of the pulse peak value without filter capacitor (CFIL)

Data Sheet S14188EJ1V0DS00

3

Share Link: