UPD17072GB-XXX-9EU 查看數據表（PDF） - NEC => Renesas Technology
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UPD17072GB-XXX-9EU
NEC => Renesas Technology
UPD17072GB-XXX-9EU Datasheet PDF : 226 Pages
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µPD17072,17073
14.5 Presettable Shift Register ...................................................................................................................... 117
14.6 Wait Control Block ................................................................................................................................. 117
14.7 Serial Interface Operation ..................................................................................................................... 118
14.8 Notes on Setting and Reading Data ..................................................................................................... 122
14.9 Operational Outline of Serial Interface ................................................................................................. 123
14.10 Status on Reset ..................................................................................................................................... 125
15. PLL FREQUENCY SYNTHESIZER ................................................................................................ 126
15.1 General ................................................................................................................................................... 126
15.2 Input Selector Block and Programmable Divider ................................................................................. 127
15.3 Reference Frequency Generator ........................................................................................................... 133
15.4 Phase Comparator (φ-DET), Charge Pump, and Unlock FF ............................................................... 135
15.5 PLL Disable Status ................................................................................................................................ 139
15.6 Use of PLL Frequency Synthesizer ...................................................................................................... 140
15.7 Status on Reset ..................................................................................................................................... 143
16. INTERMEDIATE FREQUENCY (IF) COUNTER ............................................................................. 144
16.1 Outline of Intermediate Frequency (IF) Counter .................................................................................. 144
16.2 IF Counter Input Selector Block and Gate Time Control Block ........................................................... 145
16.3 Start Control Block and IF Counter ....................................................................................................... 147
16.4 Using IF Counter .................................................................................................................................... 152
16.5 Status at Reset ...................................................................................................................................... 154
17. BEEP ................................................................................................................................................ 155
17.1 Configuration and Function of BEEP .................................................................................................... 155
17.2 Output Wave Form of BEEP ................................................................................................................. 156
17.3 Status at Reset ...................................................................................................................................... 157
18. LCD CONTROLLER/DRIVER ......................................................................................................... 158
18.1 Outline of LCD Controller/Driver ........................................................................................................... 158
18.2 LCD Drive Voltage Generation Block .................................................................................................... 159
18.3 LCD Segment Register .......................................................................................................................... 160
18.4 Common Signal Output and Segment Signal Output Timing Control Blocks ..................................... 162
18.5 Common Signal and Segment Signal Output Waves .......................................................................... 163
18.6 Using LCD Controller/Driver .................................................................................................................. 165
18.7 Status at Reset ...................................................................................................................................... 167
19. STANDBY ........................................................................................................................................ 168
19.1 General ................................................................................................................................................... 168
19.2 Halt Function .......................................................................................................................................... 170
19.3 Clock Stop Function ............................................................................................................................... 178
19.4 Device Operations in Halt and Clock Stop Statuses ............................................................................ 181
19.5 Note on Processing of Each Pin in Halt and Clock Stop Statuses ..................................................... 182
19.6 Device Control Function by CE Pin ...................................................................................................... 185
19.7 Low-Speed Mode Function .................................................................................................................... 187
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