UPD70F3210YGKA-9EU 查看數據表（PDF） - NEC => Renesas Technology

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UPD70F3210YGKA-9EU

32-Bit Single-Chip Microcontrollers

NEC => Renesas Technology 

Major Revisions in This Edition (1/2)

Pages

Description

Throughout • Addition of the following special quality grade products.

µPD703208(A), 703208Y(A), 703209(A), 703209Y(A), 703210(A), 703210Y(A), 703212(A), 703212Y(A),

703213(A), 703213Y(A), 703214(A), 703214Y(A), 703216(A), 703216Y(A), 703217(A), 703217Y(A), 70F3210(A),

70F3210Y(A), 70F3214(A), 70F3214Y(A), 70F3217(A), 70F3217Y(A)

p. 33

Addition of Caution in 1.2.4 Pin configuration (top view) (V850ES/KF1)

p. 41

Addition of Caution in 1.3.4 Pin configuration (top view) (V850ES/KG1)

p. 49

Addition of Caution in 1.4.4 Pin configuration (top view) (V850ES/KJ1)

p. 55

Addition of description in CHAPTER 2 PIN FUNCTIONS and addition of Table 2-1 Pin I/O Buffer Power

Supplies

pp.93, 95 Modification of description on recommended connection of P70 to P77, P78 to P715, IC, VPP, and XT1 in 2.4 Pin

I/O Circuits and Recommended Connection of Unused Pins

p. 134

Modification of description in 3.4.8 (2) Access to special on-chip peripheral I/O registers

p. 285

Modification of description in 5.11 Bus Timing

p. 291

Addition of 5.12 Cautions

p. 292

Addition of description on the main clock oscillator in 6.1 Overview

p. 293

Addition of description in 6.2 (1) Main clock oscillator

p. 296

Addition of Caution 3 in 6.3 (1) Processor clock control register (PCC)

p. 302

Addition of description in CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05

p. 306

Modification of description of Caution 4 in 7.2 (2) 16-bit timer capture/compare register 0n0 (CR0n0)

p. 307

Modification of description of Caution 4 in 7.2 (3) 16-bit timer capture/compare register 0n1 (CR0n1)

p. 311

Modification of description of Caution 1 in 7.3 (3) 16-bit timer output control register 0n (TOC0n)

p. 319

Addition of setting procedures and modification of description in 7.4.1 Operation as interval timer (16 bits)

p. 322

Addition of setting procedures in 7.4.2 PPG output operation

p. 324

Addition of Figure 7-6 Configuration of PPG Output

p. 325

Addition of Figure 7-7 PPG Output Operation Timing

p. 326

Addition of setting procedures in 7.4.3 Pulse width measurement

p. 334

Addition of setting procedures and addition of Caution 2 in 7.4.4 Operation as external event counter (16-bit

timer/event counters 00, 01, 04 and 05 only)

p. 337

Addition of setting procedures and addition of Caution in 7.4.5 Square-wave output operation (16-bit

timer/event counters 04 and 05 only)

p. 340

Addition of setting procedures in 7.4.6 One-shot pulse output operation

p. 340

Addition of Caution 2 in 7.4.6 (1) One-shot pulse output with software trigger

p. 342

Addition of Caution 2 in 7.4.6 (2) One-shot pulse output with external trigger

p. 349

Addition of Caution in 7.4.7 (10) (b) When setting CR0n0, CR0n1 to compare mode

p. 350

Addition of description in CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51

p. 369

Addition of description in CHAPTER 9 8-BIT TIMERS H0 AND H1

p. 373

Addition of Caution 3 in 9.3 (1) (a) 8-bit timer H mode register 0 (TMHMD0)

p. 374

Addition of Caution 3 in 9.3 (1) (b) 8-bit timer H mode register 1 (TMHMD1)

p. 386

Addition of Caution 2 in Figure 9-7 Transfer Timing

p. 388

Addition of Caution 4 in 9.4.3 (4) Timing chart

p. 427

Addition of 13.4 Relationship Between Analog Input Voltage and A/D Conversion Result

6

User’s Manual U15862EJ3V0UD

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