UPD703214 查看數據表（PDF） - NEC => Renesas Technology

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UPD703214

32-Bit Single-Chip Microcontrollers

NEC => Renesas Technology 

4.3.9 Port CS ........................................................................................................................................ 125

4.3.10 Port CT ........................................................................................................................................ 127

4.3.11 Port DH ........................................................................................................................................ 129

4.3.12 Port DL......................................................................................................................................... 131

4.4 Block Diagrams ........................................................................................................................ 134

4.5 Port Register Setting When Alternate Function Is Used...................................................... 160

4.6 Cautions .................................................................................................................................... 166

4.6.1 Cautions on bit manipulation instruction for port n register (Pn) .................................................. 166

4.6.2 Hysteresis characteristics ............................................................................................................ 167

CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 168

5.1 Features .................................................................................................................................... 168

5.2 Bus Control Pins ...................................................................................................................... 169

5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed................... 170

5.2.2 Pin status in each operation mode............................................................................................... 170

5.3 Memory Block Function........................................................................................................... 171

5.3.1 Chip select control function.......................................................................................................... 172

5.4 External Bus Interface Mode Control Function..................................................................... 172

5.5 Bus Access ............................................................................................................................... 173

5.5.1 Number of clocks for access........................................................................................................ 173

5.5.2 Bus size setting function .............................................................................................................. 173

5.5.3 Access by bus size ...................................................................................................................... 174

5.6 Wait Function............................................................................................................................ 181

5.6.1 Programmable wait function ........................................................................................................ 181

5.6.2 External wait function................................................................................................................... 182

5.6.3 Relationship between programmable wait and external wait ....................................................... 183

5.6.4 Programmable address wait function........................................................................................... 184

5.7 Idle State Insertion Function................................................................................................... 185

5.8 Bus Hold Function ................................................................................................................... 186

5.9

5.10

5.11

5.8.1 Functional outline......................................................................................................................... 186

5.8.2 Bus hold procedure...................................................................................................................... 187

5.8.3 Operation in power save mode .................................................................................................... 187

Bus Priority ............................................................................................................................... 188

Bus Timing................................................................................................................................ 189

Cautions .................................................................................................................................... 195

CHAPTER 6 CLOCK GENERATION FUNCTION............................................................................... 196

6.1 Overview ................................................................................................................................... 196

6.2 Configuration............................................................................................................................ 197

6.3 Registers ................................................................................................................................... 199

6.4 Operation .................................................................................................................................. 203

6.4.1 Operation of each clock ............................................................................................................... 203

6.4.2 Clock output function ................................................................................................................... 203

6.4.3 External clock input function ........................................................................................................ 203

6.5 PLL Function ............................................................................................................................ 204

6.5.1

6.5.2

6.5.3

Overview...................................................................................................................................... 204

Register ....................................................................................................................................... 204

Usage .......................................................................................................................................... 205

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User’s Manual U16890EJ1V0UD

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