UPD72001C-11 查看數據表（PDF） - NEC => Renesas Technology
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UPD72001C-11 Datasheet PDF : 40 Pages
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µPD72001-11, 72001-A8
Capacitance (TA = 25 °C, VDD = 0 V)
Parameter
Input capacitance
I/O capacitance
Symbol
CIN
CIO
Condition
fC = 1 MHz
Pins other than test pin: 0 V
AC Characteristics
µPD72001-11 (TA = –40 to +85 °C, VDD = 5 V ± 10 %)
System interface:
Parameter
Symbol
Condition
Clock cycle
tCYK
Clock high-pulse width
tWKH
Clock low-pulse width
tWKL
Clock rise time
tKR
1.5 V → 3.0 V
Clock fall time
tKF
3.0 V → 1.5 V
Address setup time (vs. RD ↓)
tSAR
Address hold time (vs. RD ↑)
tHRA
RD pulse width
tWRL
Address → data output delay time
tDAD
TA = –10 to +70 °C
TA = –40 to +85 °C
RD → data output delay time
tDRD
TA = –10 to +70 °C
TA = –40 to +85 °C
RD → data float delay time
tFRD
Address setup time (vs. WR ↓)
tSAW
Address hold time (vs. WR ↑)
tHWA
WR pulse width
tWWL
Data setup time (vs. WR ↑)
tSDW
TA = –10 to +70 °C
TA = –40 to +85 °C
Data hold time (vs. WR ↑)
tHWA
Recovery time between RD and WR
tRV
MIN. MAX. Unit
10
pF
20
pF
Rated Value
Unit
MIN. MAX.
90
2 000 ns
40
1 000 ns
40
1 000 ns
10
ns
10
ns
0
ns
0
ns
120
ns
100
ns
110
100
ns
110
10
85
ns
0
ns
0
ns
120
ns
100
ns
90
0
ns
140
ns
16
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