UPD75048CW 查看數據表（PDF） - NEC => Renesas Technology

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产品描述 (功能)

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UPD75048CW

4-BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

µPD75048

6.2 CLOCK GENERATOR CIRCUIT

The operation of the clock generator circuit is determined by the processor clock control regiser (PPC)

and system clock control register (SCC).

This circuit can generate two types of clocks: main system clock and subsystem clock.

In addition, it can also change the instruction execution time.

• 0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz)

• 122µs (subsystem clock: 32.768 kHz)

XT1

VDD

Subsystem fXT

clock

Watch timer

XT2

oscillator

. Multi-function timer

. Basic interval timer (BT)

. Timer/event counter

. Serial interface

. Watch timer

. A/D converter

(successive approximation)

. INT0 noise rejecter circuit

. Clock output circuit

X1

VDD

Main system fX

clock

X2

oscillator

1/2 1/16

1/2 to 1/4096

Frequency divider

WM.3

SCC

SCC3

SCC0

PCC

PCC0

4

HALT*

STOP*

PCC1

PCC2

PCC3

Oscillator

disable

signal

HALT F/F

S

R

Q

Frequency

divider

1/4

Φ

. CPU

. INT0 noise

rejecter circuit

. Clock output

circuit

PCC2, PCC3

clear signal

STOP F/F

Q

S

Wait release

signal from BT

RESET signal

R

Standby release

signal from interrupt

control circuit

Remarks1: fX = Main system clock frequency

2: fXT = Subsystem clock frequency

3: Φ = CPU clock

4: PCC: Processor clock control register

5: SCC: System clock control register

6: * indicates instruction execution.

7: One clock cysle (tCY) of Φ is one machine cycle of an instruction. For tCY, refer to AC

characteristics in 11. ELECTRICAL SPECIFICATIONS.

Fig. 6-1 Clock Generator Block Diagram

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