UPD75206CW 查看數據表（PDF） - NEC => Renesas Technology

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UPD75206CW

4-BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

µPD75206

4. µPD75206 ARCHITECTURE AND MEMORY MAP

The µPD75206 has the following three architectural features.

• Data memory bank configuration: Static RAM (320 words x 4 bits)

Display data memory (49 words x 4 bits)

Peripheral hardware (128 x 4 bits)

• General register bank configuration: 8 x 4 banks (Operated in 4 bits)

4 x 4 banks (Operated in 8 bits)

• Memory mapped I/O

Figures 4-1, 4-2 shows memory maps of µPD75206.

Fig. 4-1 Program Memory Map

Address

0000H

7

6

MBE RBE

0 0 0 2 H MBE RBE

0 0 0 4 H MBE RBE

0 0 0 6 H MBE RBE

0 0 0 8 H MBE RBE

0 0 0 A H MBE RBE

0 0 0 C H MBE RBE

0 0 0 E H MBE RBE

0020H

007FH

0080H

5

0

0 Internal Reset Start Address (Most Significant 5 Bits)

Internal Reset Start Address (Least Significant 8 Bits)

0 INTBT/INT4 Start Address (Most Significant 5 Bits) CALLF

INTBT/INT4 Start Address (Least Significant 8 Bits) !faddr

0 INT0 Start Address

(Most Significant 5 Bits) Instruction

INT0 Start Address

(Least Significant 8 Bits) Entry Address

0 INT1 Start Address

(Most Significant 5 Bits)

INT1 Start Address

(Least Significant 8 Bits)

0 INTSIO Start Address

(Most Significant 5 Bits)

INTSIO Start Address

0 INTT0 Start Address

INTT0 Start Address

0 INTTPG Start Address

INTTPG Start Address

0 INTKS Start Address

INTKS Start Address

(Least Significant 8 Bits)

(Most Significant 5 Bits)

(Least Significant 8 Bits)

(Most Significant 5 Bits)

(Least Significant 8 Bits)

(Most Significant 5 Bits)

(Least Significant 8 Bits)

BRCB

!caddr

Instruction

Branch Address

CALL !addr

Instruction

Subroutine Entry

Address

BR !addr

Instruction

Branch Address

GETI Instruction Reference Table

BR $addr Instruction

Relative Branch

Address

(-15 to -1 and +2 to +16)

07FFH

0800H

0FFFH

1000H

Branch Destination

Address and

Subroutine Entry

Address to be Set

by GETI Instruction

177FH

Remarks In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC

changed is enabled by BR PCDE and BR PCXA instructions.

12

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