UPD75206CW 查看數據表（PDF） - NEC => Renesas Technology

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UPD75206CW

4-BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

µPD75206

5.2 CLOCK GENERATOR CIRCUIT

The operation of the clock generator circuit is determined by the processor clock control register (PPC) and

system clock control register (SCC).

This circuit can generate two types of clocks: main system clock and subsystem clock.

In addition, it can also change the instruction execution time.

• 0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz)

• 122 µs (subsystem clock: 32.768 kHz)

XT1

XT2

X1

X2

SCC

SCC3

SCC0

PCC

PCC0

Fig. 5-1 Clock Generator Block Diagram

Subsystem fXT

Clock

Generator

Main System

Clock

Generator fX

Oscillation

Stop

Watch Timer

Timer/Pulse

Generator

fXX

1/2 1/6

• FIP Controller

• Basic Interval Timer (BT)

• Timer/Event Counter

• Serial Interface

• Watch Timer

• INT0 Noise Eliminator

1/8~1/4096

Frequency Divider

Frequency

Divider

1/4

Φ

• CPU

• INT0 Noise Eliminator

• INT1 Noise Eliminator

PCC1

4

PCC2

HALT*

PCC3

STOP*

HALT F/F

S

RQ

PCC2 and

PCC3

Clear

* Instruction execution

STOP F/F

QS

R

Wait Release Signal from BT

RES Signal (Internal Reset)

Standby Release Signal from

Interrupt Control Circuit

Remarks 1. fX = Main system clock frequency

2. fXT = Subsystem clock frequency

3. fXX = System clock frequency

4. Φ = CPU clock

5. PCC: Processor clock control register

6. SCC: System clock control register

7. 1 clock cycle (tCY) of Φ is 1 machine cycle of an instruction. For tCY, see ”AC Characteristics“ in 12. 5

ELECTRICAL SPECIFICATIONS.

15

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