UPD75237GJ-XXX-5BG 查看數據表（PDF） - NEC => Renesas Technology

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UPD75237GJ-XXX-5BG

4-BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

µPD75237

2. µPD75237 ARCHITECTURE AND MEMORY MAP

The µPD75237 has the following three architectural features.

(a) Data memory bank configuration

(b) General register bank configuration

(c) Memory mapped I/O

Each feature is outlined below.

2.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODE

As shown in Fig. 2-1, the µPD75237 incorporates a static RAM (928 words × 4 bits) at addresses 000H to 19FH

and 200H to 3FFH in the data memory space and a display data memory (96 words × 4 bits) at addresses 1A0H to

1FFH and peripheral hardware (input/output ports, timers, etc.) at addresses F80H to FFFH. For addressing of this

12-bit address data memory space, the memory bank has a configuration wherein the lower 8 bits are directly or

indirectly specified by an instruction and the higher 4-bit address is specified by a memory bank (MB).

A memory bank enable flag (MBE) and a memory bank select register (MBS) are incorporated to specify the

memory bank (MB) and addressing operations shown in Fig. 2-1 and Table 2-1 can be carried out. (MBS is a register

to select the memory bank and can set 0, 1, 2, 3 and 15. MBE is a flag to determine whether the memory bank selected

by MBS should be validated or not. Since MBE is automatically saved/reset for interrupt or subroutine processing,

it can be freely set for either processing.)

For data memory space addressing, set MBE = 1 normally and manipulate the memory bank static RAM specified

by MBS. Efficient programming is possible by using the MBE = 0 or MBE = 1 mode for each program processing.

MBE = 0 mode

MBE = 1 mode

Applicable Program Processing

Interrupt service

Processing of repeating built-in hardware manipulation and static RAM manipulation

Subroutine processing

Normal program processing

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