UPD77019-013 查看數據表（PDF） - NEC => Renesas Technology

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UPD77019-013

16 bits, Fixed-point Digital Signal Processor

NEC => Renesas Technology 

PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

µPD77019-013

16 bits, Fixed-point Digital Signal Processor

The µPD77019-013 is a masked 16 bits fixed-point DSP (Digital Signal Processor) developed for digital signal

processing with its demand for high speed and precision.

The µPD77019-013 internal ROM area is masked already by the void code to use as RAM based DSP without mask

code ordering process. Also the µPD77019-013 can operate as simplified evaluate chip for as the µPD7701x family.

About mask ROM and mask option, there are following differences between the µPD77019-013 and µPD77019.

PLL clock multiple rate

Crystal resonator

connection

Clock Input pin

Clock output pin

Internal mask ROM

Self boot

Fixed to 4

µPD77019-013

Disable (PLL clock multiple rate is fixed to 4.)

External clock is connected to the X1 pin.

Leave the X2 pin open.

Output internal system clock.

Not available (already masked by the void

code)

Enable to boot from external data area (Boot

information data is masked.) Refer to 2.6

Boot Function.

µPD77019

Variable multiple rate (1, 2, 3, 4, 8) by mask

option

Enable (PLL clock multiple rate is set to 1 by

mask option.)

External clock is connected to the X1 pin.

Crystal is connected between the X1 pin and

X2 pin.

Low level fixed, or internal system clock

output is selectable by mask option.

Coding user program or data when ordering

mask ROM.

Enable to boot from internal data ROM or

external data area.

ORDERING INFORMATION

Part Number

µPD77019GC-013-9EU

Package

100-pin plastic TQFP (FINE PITCH) (14 × 14 mm)

The µPD7701x family consists of the µPD77016, 77015, 77017, 77018, 77018A and µPD77019.

The information in this document is subject to change without notice.

Document No. U13053EJ1V0DS00 (1st edition)

Date Published March 1998 N CP(K)

Printed in Japan

©

1998

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