UPSD3233 查看數據表（PDF） - STMicroelectronics

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UPSD3233

Flash Programmable System Devices with 8032 Microcontroller Core and 64 Kbit SRAM

STMicroelectronics 

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

Table 129. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices)

Symbol

Parameter

Conditions

Min

Max

PT

Aloc

Turbo Slew

Off rate(1)

Unit

Maximum Frequency

External Feedback

1/(tS+tCO)

22.2

MHz

fMAX

Maximum Frequency

Internal Feedback (fCNT)

1/(tS+tCO–10)

28.5

MHz

Maximum Frequency

Pipelined Data

1/(tCH+tCL)

40.0

MHz

tS

Input Setup Time

20

+ 4 + 20

ns

tH

Input Hold Time

0

ns

tCH

Clock High Time

Clock Input

15

ns

tCL

Clock Low Time

Clock Input

10

ns

tCO

Clock to Output Delay

Clock Input

25

– 6 ns

tARD

CPLD Array Delay

Any macrocell

25

+4

ns

tMIN

Minimum Clock Period(2)

tCH+tCL

25

ns

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.

2. CLKIN (PD1) tCLCL = tCH + tCL.

Figure 80. Asynchronous RESET / Preset

tARPW

RESET/PRESET

INPUT

REGISTER

OUTPUT

tARP

AI02864

Figure 81. Asynchronous Clock Mode Timing (product term clock)

tCHA

tCLA

CLOCK

tSA tHA

INPUT

REGISTERED

OUTPUT

tCOA

AI02859

154/170

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