UPSD3233 查看數據表（PDF） - STMicroelectronics

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UPSD3233

Flash Programmable System Devices with 8032 Microcontroller Core and 64 Kbit SRAM

STMicroelectronics 

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

Figure 84. Peripheral I/O WRITE Timing

ALE

A /D BUS

ADDRESS

DATA OUT

tWLQV (PA)

tWHQZ (PA)

WR

tDVQV (PA)

PORT A

DATA OUT

Table 138. Port A Peripheral Data Mode WRITE Timing (5V Devices)

Symbol

Parameter

Conditions

Min

tWLQV–PA

WR to Data Propagation Delay

tDVQV–PA

Data to Port A Data Propagation Delay

(Note 1)

tWHQZ–PA WR Invalid to Port A Tri-state

Note: 1. Data stable on Port 0 pins to data on Port A.

Table 139. Port A Peripheral Data Mode WRITE Timing (3V Devices)

Symbol

Parameter

Conditions

Min

tWLQV–PA

WR to Data Propagation Delay

tDVQV–PA

Data to Port A Data Propagation Delay

(Note 1)

tWHQZ–PA WR Invalid to Port A Tri-state

Note: 1. Data stable on Port 0 pins to data on Port A.

AI06611

Max

Unit

25

ns

22

ns

20

ns

Max

Unit

42

ns

38

ns

33

ns

159/170

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