V386GLF 查看數據表（PDF） - Integrated Circuit Systems
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V386GLF Datasheet PDF : 10 Pages
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V386
8-BIT LVDS RECEIVER FOR VIDEO
Clock
Previous Cycle
TCLK
Next Cycle
Data
Rspos0 Min
Rspos0 Max
Rspos1 Min
Rspos1 Max
Rspos2 Min
Rspos2 Max
Rspos3 Min
Rspos3 Max
Rspos4 Min
Rspos4 Max
Rspos5 Min
Rspos5 Max
Rspos6 Min
Rspos6 Max
Figure 7. V386 LVDS Input Strobe Position
RCK+/RCK-
RX[n]+/RX[n]-
N = 0, 1, 2, 3
Figure 8. Receiver Input Skew Margin
Skew Margin
V386 Datasheet
9
5/25/05
Revision 2.0
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com
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