DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

V436664Z24VXBG-10PC 查看數據表(PDF) - Mosel Vitelic Corporation

零件编号
产品描述 (功能)
生产厂家
V436664Z24VXBG-10PC
Mosel-Vitelic
Mosel Vitelic Corporation  Mosel-Vitelic
V436664Z24VXBG-10PC Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MOSEL VITELIC
V436664Z24V
Serial Presence Detect Information
A serial presence detect storage device - E2PROM -
is assembled onto the module. Information about the
module configuration, speed, etc. is written into the
SPD-Table for modules:
E2PROM device during module production using a se-
rial presence detect protocol (I2C synchronous 2-wire
bus)
Byte Num-
ber
Function Described
SPD Entry Value
0
Number of SPD bytes
128
1
Total bytes in Serial PD
256
2
Memory Type
SDRAM
3
Number of Row Addresses (without BS bits)
13
4
Number of Column Addresses (for x8 SDRAM)
10
5
Number of DIMM Banks
2
6
Module Data Width
64
7
Module Data Width (continued)
0
8
Module Interface Levels
LVTTL
9
SDRAM Cycle Time at CL=3
7.5 ns/10.0 ns
10
SDRAM Access Time from Clock at CL=3
5.4 ns/10.0ns
11
Dimm Config (Error Det/Corr.)
none
12
Refresh Rate/Type
Self-Refresh, 7.8 µs
13
SDRAM width, Primary
x8
14
Error Checking SDRAM Data Width
n/a / x8
15
Minimum Clock Delay from Back to Back Ran-
tccd = 1 CLK
dom Column Address
16
Burst Length Supported
1, 2, 4 & 8
17
Number of SDRAM Banks
4
18
Supported CAS Latencies
CL = 2 / 3
19
CS Latencies
CS Latency = 0
20
WE Latencies
WL = 0
21
SDRAM DIMM Module Attributes
Non Buffered/Non Reg.
22
SDRAM Device Attributes: General
Vcc tol ± 10%
23
Minimum Clock Cycle Time at CAS Latency = 2
7.5 ns/10.0 ns
-75PC
80
08
04
0D
0A
02
40
00
01
75
54
00
82
08
00
01
0F
04
06
01
01
00
0E
75
Hex Value
-75
80
08
04
0D
0A
02
40
00
01
75
54
00
82
08
00
01
0F
04
06
01
01
00
0E
A0
-10PC
80
08
04
0D
0A
02
40
00
01
A0
60
00
82
08
00
01
0F
04
06
01
01
00
0E
A0
24
Maximum Data Access Time from Clock for CL
=2
5.4 ns/6.0 ns
54
60
60
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
00
00
26
Maximum Data Access Time from Clock at CL
Not Supported
00
00
00
=1
27
Minimum Row Precharge Time
15 ns / 20 ns
0F
14
14
28
Minimum Row Active to Row Active Delay tRRD 14 ns/15 ns/16 ns
0E
0F
10
V436664Z24V Rev. 1.2 February 2002
4

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]