V82658B04SXTG-A1 查看數據表（PDF） - Mosel Vitelic Corporation
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V82658B04SXTG-A1 Datasheet PDF : 14 Pages
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MOSEL VITELIC
V82658B04S
DDR SDRAM IDD SPEC TABLE
Symbol
B1(DDR266@CL=2)
Typical
Worst
IDD0
410
470
IDD1
510
590
IDD2P
110
130
IDD2F
210
250
IDD2Q
170
190
IDD3P
150
170
IDD3N
230
270
IDD4R
730
850
IDD4W
770
910
IDD5
770
870
IDD6 Normal
8
8
Low power
4
4
IDD7A
1390
1610
B0(DDR266@CL=2.5) A1(DDR200@CL=2)
Typical
Worst Typical Worst
410
470
370
410
510
590
470
550
110
130
90
110
210
250
190
210
170
190
150
170
150
170
130
150
230
270
190
230
730
850
610
750
770
910
650
810
770
870
730
810
8
8
8
8
4
4
4
4
1390
1610
1130
1330
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
V82658B04S Rev. 1.2 March 2002
9
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