VG26S17400FJ-5 查看數據表（PDF） - Vanguard International Semiconductor
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VG26S17400FJ-5 Datasheet PDF : 25 Pages
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VIS
Read Cycle
Parameter
Access time from RAS
Access time from CAS
Access time from column address
Access time from OE
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Output buffer turn-off time
Output buffer turn-off time from OE
Write Cycle
Parameter
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
Data-in hold time
Read - Modigy - Write Cycle
Parameter
Read - modify - write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
OE hold time from WE
VG26(V)(S)17400FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Symbol
tRAC
tCAC
tAA
tOEA
tRCS
tRCH
tRRH
tOFF
tOEZ
VG26 (V) (S) 17400E
-5
-6
Unit
Min Max Min Max
-
50
- 60 ns
- 13
- 15 ns
- 25
- 30 ns
- 12
- 15 ns
0
-
0
- ns
0
-
0
- ns
10
- 10
- ns
0 12
0 12
0 15 ns
0
15 ns
Notes
12
13,14
14,15
7
10,16
16
17
17
Symbol
tWCS
tWCH
tWP
tRWL
tCWL
tDS
tDH
VG26 (V) (S) 17400E
-5
-6
Unit
Min Max Min Max
0
-
0
- ns
8
- 10
- ns
8
- 10
- ns
13
- 15
- ns
8
- 10
- ns
0
-
0
- ns
8
- 10
- ns
Notes
7,18
19
19
Symbol
tRWC
tRWD
tCWD
tAWD
tOEH
VG26 (V) (S) 17400E
-5
-6
Unit
Min Max Min Max
108
- 133
- ns
64
- 77
- ns
26
- 32
- ns
39
- 47
- ns
8
- 10
- ns
Notes
18
18
18
Document :
Rev.
Page 11
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