VORTEX86SX 查看數據表（PDF） - Unspecified

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VORTEX86SX

32-BIT x86 Embedded SoC

Unspecified 

C20, B20, A21

A22, A23, A24,

A25, B26, D20,

E20, C21, B21,

C22, B22, C23,

B23, E24, E25,

E26, H22, G23,

F26, F25, H21,

G25, J22, G26,

H25, H26, J25,

J26, H24

B25, B24, G22,

F24

C24

C25

AD[31:0]

CBE_[3:0]

FRAME_

IRDY_

C26

TRDY_

D24

DEVSEL_

D25

STOP_

G24

PAR

H23

INTA_

F19

INTB_

F20

INTC_

E19

INTD_

Vortex86SX

32-Bit x86 Embedded SoC

PCI Address and Data. The standard PCI address and data lines. The

I/O address is driven with PCI Frame assertion and data is driven or received in

the following clocks.

Bus Command and Byte Enables. During the address phase, C/BE_n[3:0]

I/O define the Bus Command. During the data phase, C/BE[3:0]_n define the Byte

Enables.

I/O

PCI Frame. This pin is driven by a PCI master to indicate the beginning and

duration of a PCI transaction.

PCI Initiator Ready. This pin is asserted low by the master to indicate that it

I/O

is able to transfer the current data transfer. A data was transferred if both

IRDY_n and TRDY_n are asserted low during the rising edge of the PCI

clock.

PCI Target Ready. This pin is asserted low by the target to indicate that it is

I/O

able to receive the current data transfer. A data was transferred if both

IRDY_n and TRDY_n are asserted low during the rising edge of the PCI

clock.

I/O

Device Select. This pin is driven by the devices which have decoded the

addresses belonging to them.

I/O

PCI Stop. This pin is asserted low by the target to indicate that it is unable to

receive the current data transfer.

PCI Parity. This pin is driven to even parity by PCI master over the AD[31:0]

I/O

and C/BE_n[3:0] bus during address and write data phases. It should be

pulled high through a weak external pull-up resistor. The target drives parity

during data read.

I

PCI INTA_. PCI interrupt input A. It connects to PCI INTA_n when normal

modes of PCI Interrupts are supported.

I

PCI INTB_. PCI interrupt input B. It connects to PCI INTB_n when normal

modes of PCI Interrupts are supported.

I

PCI INTC_. PCI interrupt input C. It connects to PCI INTC_n when normal

modes of PCI Interrupts are supported.

I

PCI INTD_. PCI interrupt input D. It connects to PCI INTD_n when normal

modes of PCI Interrupts are supported.

z EXTERNAL SPI/PORT[3-0] Interface (4 PINs)

PIN No.

W21

W22

Y21

Y22

Symbol

E_SPI_CS_/GPIO_P3[0]

E_SPI_CLK/GPIO_P3[1]

E_SPI_DO/GPIO_P3[2]

E_SPI_DI/GPIO_P3[3]

Type

Description

I/O

External SPI Chip Select

General-Purpose Input/Output P3[0]

I/O

External SPI Clock

General-Purpose Input/Output P3[1]

I/O

External SPI Data Ouput

General-Purpose Input/Output P3[2]

I/O

External SPI Data Input

General-Purpose Input/Output P3[3]

z ISA Bus Interface ( 87 PINs)

PIN No.

Symbol

AA13

AE16, AF16, AD10,

AF15, AF14, AE11,

AE10, AD12,Y6,

AD14, Y4, AA14,

IOCHCK_

SD[15:0]

10

Type

Description

I

I/O Channel Check. Provides the system board with parity (error) information

about memory or devices on the I/O channel.

ISA high and low byte slot data bus. These are the system data lines.

I/O These signals read data and vectors into CPU during memory or I/O read

cycles or interrupt acknowledge cycles and outputs data from CPU during

Vortex86SX Brief Datasheet

Version 1.001

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