VORTEX86SX 查看數據表（PDF） - Unspecified

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VORTEX86SX

32-BIT x86 Embedded SoC

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Vortex86SX

32-Bit x86 Embedded SoC

Bank Address BA[1:0]. These pins are connected to SDRAM/DDR as bank

address pins.

Strap[17:16]. Memory Select, Default pull high.

F12, D12

BA[1:0]/Strap[17:16] O

Strap[17]

0

Strap[16] DRAM Select

0

SDRAM

0

1

Reserved

1

0

DDR

C12

D16, C17, C14,

D15, C15, E14,

C16, E15, B15,

A13, A14, A17,

A16, A15, B16,

B17

A10

BA[2]

MD[15:0]

MA[0]

A11

MA[1]/Strap[1]

C9

MA[2]

1

1

DDRII (Default)

O

Bank Address [2]. These pins are connected to SDRAM/DDR as bank

address pins.

I/O

Memory Data MD[15:0]. These pins are connected to the SDRAM/DDR data

bus.

O

Memory Address MA[0]. Normally, these pins are used as the row and

column address for SDRAM/DDR.

Memory Address MA[1]. Normally, these pins are used as the row and

column address for SDRAM/DDR.

O Strap[1].

Pull it high to enable GPIO2. Default pull high.

Pull it low to enable Address[31:24].

Memory Address MA[2]. Normally, these pins are used as the row and

O column address for SDRAM/DDR.

Memory Address MA[3]. Normally, these pins are used as the row and

column address for SDRAM/DDR.

Strap[3]. PLL_TEST_OUT_EN_, Default pull low.

B10

MA[3] /Strap[3]

O Pull it high to enable PLL_TEST_OUT_EN_.

Pull it low to disable PLL_TEST_OUT_EN_.

C10

C11,B12,B11

F9

MA[4] /Strap[4]

MA[7:5]/Strap[7:5]

MA[8]/Strap[8]

Memory Address MA[4]. Normally, these pins are used as the row and

column address for SDRAM/DDR.

Strap[4]/[10]. SDRAM/DDR clock, Default pull high.

Strap[10]

O

0

Strap[4]

0

SDRAM clock

100MHz

0

1

133MHz (Internal default)

1

0

166MHz

1

1

200MHz

Memory Address MA[7:5]. Normally, these pins are used as the row and

column address for SDRAM/DDR.

Strap[7:5] / CPU Clock

3b’000 / Bypass mode

3b’001 / SYN_DISABLE_ (CPU clock same to SDRAM Clock)

I/O

3b’010 / 233MHz

3b’011 / 266MHz

3b’100 / 300MHz (Internal default)

3b’101 / 333MHz

3b’110 / 366MHz

3b’111 / 400MHz

Memory Address MA[8]. Normally, these pins are used as the row and

I/O column address for SDRAM/DDR.

Strap[8]. Pull it high to enable Vortex86SX JTAG. Default internal pull-high.

8

Vortex86SX Brief Datasheet

Version 1.001

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