VRS51L1050-25-PG 查看數據表（PDF） - Ramtron International Corporation

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VRS51L1050-25-PG

Versa 8051 3.3V MCU with 64KB of IAP/ISP Flash

Ramtron International Corporation 

VRS51L1050

Power Control Register

The VRS51L1050 provides two power saving modes,

idle and power down, which are controlled by the

PDOWN and IDLE bits of the PCON register at

address 87h.

TABLE 15: POWER CONTROL REGISTER (PCON) - SFR 87H

7

65

4

3

2

SMOD

GF1 GF0

1

PDOWN

0

IDLE

Bit Mnemonic Description

7 SMOD

1: Double the baud rate of the serial port

frequency that was generated by Timer 1.

0: Normal serial port baud rate generated by

Timer 1.

6

5

4

3 GF1

General Purpose Flag

2 GF0

General Purpose Flag

1 PDOWN Power down mode control bit

0 IDLE

Idle mode control bit

The SMOD bit of the PCON register controls the

oscillator divisor applied to Timer 1 when used as a

baud rate generator for the UART. Setting this bit to 1

doubles the UART’s baud rate generator frequency.

In idle mode, the processor is disabled and the

oscillator continues operating. The contents of the

SRAM, I/O state and SFR registers are maintained and

the timer and external interrupts remain operational.

The processor will be woken up when an external

event, triggering an interrupt, occurs.

In power down mode, the oscillator and peripherals are

disabled. The contents of the SRAM and the SFR

registers, however, are maintained.

Exiting Power Down

The VRS51L1050 features two options for exiting

power down mode:

• Hardware Reset

• Triggering External Interrupts INT0 or INT1

For the VRS51L1050 to exit power down mode from

an external interrupt (INT0 or INT1), the PDWAKEUP

bit of the SYSCON register must be set to 1 and the

external interrupt must be activated and configured to

be edge or level sensitive.

Since the oscillator is disabled in power down mode,

when an interrupt is received there will be a delay

before the system restarts. The length of the delay

before the device exits power down mode will be 65-

75K oscillator cycles, may vary from device to device

and depends on the crystal used (approximately 3.1ms

for a 22.1184MHz crystal and 6.2ms for a 11.0592MHz

crystal).

When the VRS51L1050 exits power down mode as a

result of an external interrupt, the program counter will

jump to its associated interrupt service routine. Upon

completion of the interrupt service routine, the

processor will return to the main program and execute

the next instruction following the one that put the

device into power down mode. When the VRS51L1050

is in power down mode, its current consumption drops

below 20uA.

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