VSC7121 查看數據表（PDF） - Vitesse Semiconductor
零件编号
产品描述 (功能)
生产厂家
VSC7121
Vitesse Semiconductor
VSC7121 Datasheet PDF : 12 Pages
| |||
VITESSE
SEMICONDUCTOR CORPORATION
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Data Sheet
VSC7121
Table 1 is a truth table detailing the data flow through the VSC7121. Figure 1 shows a timing diagram of the
data relationship in the VSC7121. There are no critical timing (setup, hold, or delay) parameters for the
VSC7121 as this part routes the serial data encoded with the baud clock that is extracted by a Fibre Channel
receiver. The primary AC parameter of importance is the jitter or data eye degradation inserted by the port
bypass circuit. The design of the VSC7121 minimizes jitter accumulation by using fully differential circuits.
This provides for symmetric rise and fall delays as well as noise rejection.
Table 1: Truth Table
SEL1
L
L
L
L
H
H
SELECT STATE
SEL2
SEL3
L
L
L
L
L
H
H
L
L
L
H
H
SEL4
L
H
L
L
L
H
OUT
IN
SI4
SI3
SI2
SI1
SI4
DATA OUTPUTS
SO4
SO3
SO2
IN
IN
IN
IN
IN
IN
SI3
IN
IN
SI2
SI2
IN
SI1
SI1
SI1
SI3
SI2
SI1
SO1
IN
IN
IN
IN
IN
IN
IN+/-
LSI1+/-
LSI2+/-
LSI3+/-
LSI4+/-
Figure 1: Timing Waveforms
OUT+/-
LSO1+/-
LSO2+/-
LSO3+/-
LSO4+/-
T1
T2
Tjitter
Page 2
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52110-0, Rev. 4.1
8/31/98
Share Link: