VITESSE
SEMICONDUCTOR CORPORATION
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Data Sheet
VSC7121
Table 2: AC Characteristics (Over recommended operating conditions).
Parameters
T1
T2
TSDR, TSDF
Description
Flow-Through Propagation Delay
Rising Edge to Rising Edge
Flow through Propagation Delay
Falling Edge to Falling Edge
Serial data rise and fall time
Min.
—
Max.
7.0
7.0
300
Units
ns
ns
ps.
Conditions
Delay with all circuits bypassed. 75
Ohm Load
Delay with all circuits bypassed. 75
Ohm load.
20% to 80%, tested on a sample basis
Table 3: DC Characteristics (Over recommended operating conditions).
Parameters
Description
Min
Typ
Max
Units
Conditions
VIH(TTL)
Input HIGH voltage (SEL - TTL)
2.0 — 5.5
V
IIH < 6.6 mA @ VIH = 5.5 V
VIL(TTL)
Input LOW voltage (SEL - TTL)
0
— 0.8
V
—
IIH(TTL)
Input HIGH current (SEL- TTL)
—
50 500
µA
VIN = 2.4 V
IIL(TTL)
Input LOW current (SEL - TTL)
—
— -500
µA
VIN = 0.5 V
VDD
Supply voltage
3.10 — 3.50
V
VDD = 3.30V + 5%
IDD
Supply current
—
— 170
mA Outputs open, VDD = VDD max
PD
Power Dissipation
0.6
W
Outputs open, VDD = VDD max
∆VIN(DF)
Receiver differential peak-to-peak
Input Sensitivity, IN+/- & L_SIn+/-
300
2600
mVp-p
AC Coupled.
Internally biased at VDD/2
∆VOUT(L_SO)
L_SOn+/- output differential peak-
to-peak voltage swing
1000
—
2200 mVp-p 50Ω to VDD – 2.0 V
∆VOUT(OUT)
OUT+/- output differential peak-to-
peak voltage swing
1200
2200 mVp-p 50Ω to VDD – 2.0 V
Page 4
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52110-0, Rev. 4.1
8/31/98