VSC7122QM 查看數據表（PDF） - Vitesse Semiconductor
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VSC7122QM
Vitesse Semiconductor
VSC7122QM Datasheet PDF : 12 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Advance Product Information
VSC7122
The VSC7122 can be cascaded through the IN and OUT pins for arrays of disk drives greater than 4. For
disk arrays with a noninteger multiple of 4 disk drives, the unused PBC’s can be hardwired to bypass with a
external pulldown resistor.
Table 1 is a truth table detailing the data flow through the VSC7122. Figure 1 shows a timing diagram of the
data relationship in the VSC7122. There are no critical timing (setup, hold, or delay) parameters for the
VSC7122 as this part routes the serial data encoded with the baud clock that is extracted by a Fibre Channel
receiver. The primary AC parameter of importance is the jitter or data eye degradation inserted by the port
bypass circuit. The design of the VSC7122 minimizes jitter accummulation by using fully differential circuits.
This provides for symmetric rise and fall delays as well as noise rejection.
Table 1: Truth Table
SEL1
L
L
L
L
H
H
SELECT STATE
SEL2
SEL3
L
L
L
L
L
H
H
L
L
L
H
H
SEL4
L
H
L
L
L
H
OUT
IN
SI4
SI3
SI2
SI1
SI4
DATA OUTPUTS
SO4
SO3
SO2
IN
IN
IN
IN
IN
IN
SI3
IN
IN
SI2
SI2
IN
SI1
SI1
SI1
SI3
SI2
SI1
SO1
IN
IN
IN
IN
IN
IN
IN+/-
LSI1+/-
LSI2+/-
LSI3+/-
LSI4+/-
Figure 1: Timing Waveforms
OUT+/-
LSO1+/-
LSO2+/-
LSO3+/-
LSO4+/-
T1
T2
Tjitter
Page 2
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52155-0, Rev. 2.1
8/31/98
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