VSC7122 查看數據表（PDF） - Vitesse Semiconductor
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VSC7122
Vitesse Semiconductor
VSC7122 Datasheet PDF : 12 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Advance Product Information
VSC7122
Table 4: Pin Description
Pin #
9, 10
3, 4
40, 41
34, 35
27, 28
15-18
6, 7
43, 44
37, 38
30, 31
25, 24
2, 14, 20-21,
32
5, 26, 29 36,
42
1, 8, 11-13,
19, 22-23,
33, 39
Name
IN-, IN+
L_SI1-, L_SI1+
L_SI2-, L_SI2+
L_SI3-, L_SI3+
L_SI4-, L_SI4+
SEL1, SEL2,
SEL3, SEL4
L_SO1-,
L_SO1+
L_SO2-,
L_SO2+
L_SO3-,
L_SO3+
L_SO4-,
L_SO4+
OUT-, OUT+
Description
INPUT - Differential (Biased at VDD/2). Serial inputs from the downstream PBC port.
INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC
port 1.
INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC
port 2.
INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC
port 3.
INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC
port 4.
INPUT - TTL. A LOW selects the “BYPASS” mode causing the output of the previous
port to propagate to next port or OUT. When HIGH, this signal selects “NORMAL”
mode which routes the previous port to the local output, L_SOn, and routes the local
input, L_SIn, to the next port or OUT .
OUTPUT - Differential Serial output driving the local receiver corresponding to PBC
port 1.
OUTPUT - Differential Serial output driving the local receiver corresponding to PBC
port 2.
OUTPUT - Differential Serial output driving the local receiver corresponding to PBC
port 3.
OUTPUT - Differential Serial output driving the local receiver corresponding to PBC
port 4.
OUTPUT - Differential Serial output driving the upstream PBC port.
VDD
Digital Logic Power Supply. 3.3V Supply for digital logic.
VDDP
VSS
High-Speed Output Power Supply. 3.3V Supply for PECL drivers.
Ground. Ground pins are physically attached to the die mounting surface, and are an
important part of the thermal path. For best thermal performance, all ground pins should
be connected to a ground plane, using multiple vias if possible.
Page 8
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52155-0, Rev. 2.1
8/31/98
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