VSC7123RD2 查看數據表（PDF） - Vitesse Semiconductor

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VSC7123RD2

10-Bit Transceiver for Fibre Channel and Gigabit Ethernet

Vitesse Semiconductor 

VELOCITYTM

VITESSE

SEMICONDUCTOR CORPORATION

10-Bit Transceiver for Fibre

Channel and Gigabit Ethernet

Figure 4: Transmit Timing Waveforms

REFCLK

T1

T2

T(0:9)

Data Valid

Data Valid

Data Valid

Data Sheet

VSC7123

Table 2: Transmit AC Characteristics

Parameters

T1

T2

TSDR,TSDF

TLAT

RJ

DJ

Description

Min Typ Max Units

T(0:9) Setup time to the rising

edge of REFCLK

1.5

—

—

ns

T(0:9) hold time after the rising

edge of REFCLK

1.0

—

—

ns

TX+/TX- rise and fall time

—

—

300

ps

Latency from rising edge of

REFCLK to T0 appearing on

TX+/TX-

8bc

—

8bc+

4ns

ns

Transmitter Output Jitter Allocation

Random jitter (RMS)

—

5

8

ps.

Serial data output deterministic

jitter (pk-pk)

—

30

80

ps.

Conditions

Measured between the valid data

level of T(0:9) to the 1.4V point

of REFCLK.

20% to 80%, 50Ω load to

VDD-2.0.

bc = Bit clocks

ns = Nano second

Measured at SO+/-, 1 sigma

deviation of 50% crossing point.

IEEE 802.3Z Clause 38.68,

tested on a sample basis.

Page 6

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

G52212-0, Rev 4.3

03/25/01

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