VSC7123RD 查看數據表（PDF） - Vitesse Semiconductor
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VSC7123RD Datasheet PDF : 18 Pages
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VELOCITYTM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Figure 5: Receive Timing Waveforms
T4
RCLK
RCLKN
R(0:9)
Data Valid
T1
T2
Data Valid
T3
Data Valid
Table 3: Receive AC Characteristics
Parameters
T1
T2
T3
T4
TR, TF
RLAT
TLOCK(1)
Description
TTL Outputs Valid prior to
RCLK/RCLKN rise
TTL Outputs Valid after
RCLK or RCLKN rise
Delay between rising edge of
RCLK to rising edge of
RCLKN
Period of RCLK and
RCLKN
R(0:9), COMDET, SIGDET,
RCLK and RCLKN rise and
fall time
Latency from RX to R(0:9)
Data acquisition lock time
Min.
4.0
3.0
3.0
2.0
10 x TRX
-500
1.98 x
TREFCLK
—
12 bc + 1 ns
—
Max.
—
—
—
—
10 x TRX
+500
2.02 x
TREFCLK
2.4
13 bc + 9 ns
1400
Units
ns
ns
Conditions
At 1.0625Gb/s
At 1.25Gb/s
At 1.0625Gb/s
At 1.25Gb/s
ps
TRX is the bit period of the
incoming data on Rx.
ps
Whether or not locked to
serial data.
ns
Between VIL(MAX) and
VIH(MIN), into 10pf load.
bc bc = bit clock
ns ns = nano second
bc
8B/10B IDLE pattern.
bc = bit clocks
NOTE: (1) Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3.
G52212-0, Rev 4.3
03/25//01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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