VSC7126QX 查看數據表（PDF） - Vitesse Semiconductor

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VSC7126QX

Dual Speed 10-bit Serializer/Deserializer

Vitesse Semiconductor 

Datasheet

VSC7126

TBC

VITESSE

SEMICONDUCTOR CORPORATION

Figure 6: TBC Timing Waveforms

TH

TL

1.0625 Gbits/sec Fibre

Channel Transceiver

Vih(min)

Vil(max)

Table 3: Reference Clock Requirements

Parameters

Description

FR

Frequency Range

Min Max

50

55

Units

MHz

Conditions

Range over which both transmit and receive

reference clocks on any link may be centered

FO

Frequency Offset

-200 200

ppm.

Mean frequency offset between transmit and

receive reference clocks on one link

TL,TH

Pulse Width, Low / High

4.5

----

DC

TRCR,TRCF

JT

TBC duty cycle

TBC rise and fall time

Total jitter tolerance on

REFCLK

30

70

---- 2.0

---- 120

ns

Low is measured from Vil(max) to Vil(max),

High is measured from Vih(min) to Vih(min)

%

Measured at 1.5V

ns.

Between Vil(max) and Vih(min)

ps

Peak-to-peak total jitter for frequencies

between 50KHz and 7MHz

G52148-0, Rev. 4.3

3/4/99

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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