VSC7127R-QM 查看數據表（PDF） - Vitesse Semiconductor
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VSC7127R-QM Datasheet PDF : 12 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Family of Repeater/Retimer and Port
Bypass Circuits for Fibre Channel
Data Sheet
VSC7127/VSC7129
Figure 4: REFCLK Timing Waveforms *
REFCLK
VIH(MIN)
VIL(MAX)
NOTE: A reference clock must be provided to the REFCLK pin in order for the chip to power up in the right state.
Table 2: Reference Clock Requirements
Parameters
Description
FR
Frequency Range
FO
Frequency Offset
DC
TR, TF
Duty Cycle
Rise and Fall Time
Min Typ Max Units
Conditions
105
107 MHz
Maximum frequency offset
-200
200 ppm between transmit and receive
reference clocks on one link
35
65
% Measured at 1.5V
2.0
ns
Between VIL(MAX) and VIH(MIN)
DC Characteristics (Over recommended operating conditions)
Parameters
Description
Min Typ Max Units
Conditions
VOH
VOL
VIH
VIL
IIH
IIL
∆VOUT75(1)
Output HIGH voltage (TTL)
Output LOW voltage (TTL)
Input HIGH voltage (TTL)
Input LOW voltage (TTL)
Input HIGH current (TTL)
Input LOW current (TTL)
TX output differential peak-to-
peak voltage swing
2.4
V IOH = -1.0mA
0.5
V IOL = +1.0mA
2.0
5.5
V
0
0.8
V
50
500
µA VIN =2.4V
-500
µA VIN =0.5V
1200
2200 mVp-p 75Ω to VDD – 2.0 V
∆VOUT50(1)
TX output differential peak-to-
peak voltage swing
1000
2200 mVp-p 50Ω to VDD – 2.0 V
∆VIN(1)
Receiver differential peak-to-peak
input Sensitivity RX
400
2600 mVp-p Internally biased to VDD/2
VDD
Supply voltage
PD
Power dissipation
3.14
3.47
V 3.3V±5%
707
902
mW
Outputs open, VDD = VDD max.
±2%
IDD
IDDA
Current (all supplies)
Current (VDDA)
215 260
50
70
mA Outputs open, VDD = VDD max
mA VDDA = VDD max
NOTE: (1) Refer to Application Note AN-37 for details regarding differential voltage measurements.
Page 6
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52298-0, Rev 4.3
05/01/01
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