VSC7146RH 查看數據表（PDF） - Vitesse Semiconductor
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VSC7146RH Datasheet PDF : 19 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7146
2.5Gb/s, 20-Bit Transceiver
Dual Data Rate Operation
The VSC7146 performs at two data rates, full-speed (2.5 Gb/s on the serial link, 125MHz on the parallel
20-bit data bus) and half-speed (1.25 Gb/s on the serial link, 62.5 Mb/s on the parallel 20-bit data bus). To
accommodate for this, the user is provided with 3 signal pins for data rate control: TXRATE, RXRATE and
BCMN. The usage of these signals is as follows:
If BCMN = 0 (Backwards Compatibility Mode), TXRATE controls both the serializer and deserializer
speeds. TXRATE should be HIGH for full-speed operation and LOW for half-speed operation.
If BCMN = 1, TXRATE controls the serializer speed and RXRATE controls the deserializer speed.
TXRATE and/or RXRATE must be HIGH for full-speed operation and/or LOW for half-speed operation.
Table 1: Data Rate
BCMN
0
0
1
1
1
1
TXRate
1
0
0
0
1
1
RXRate
X
X
0
1
0
1
Description
Both serializer and deserializer run at full-speed.
Both serializer and deserializer run at half-speed.
Both serializer and deserializer run at half-speed.
Serializer is run at half-speed and deserializer is run at full-speed.
Serializer is run at full-speed and deserializer is run at half-speed.
Both serializer and deserializer run at full-speed.
For “comma” character (K28.5) detection, it is recommended not to use differing RXRATE inputs to actual
RX rate data reception, as shown in the Table 2 (assumes EN_CDET = 1):
Table 2: Comma Detect
RXRate
0 Half-Speed
0 Half-Speed
1 Full-Speed
1 Full-Speed
RX+/- Actual
Data Rate
2.5Gb/s
1.25Gb/s
2.5Gb/s
1.25Gb/s
“Comma” Detect
Will only detect 00/00/11/11/11/11/11 pattern as “comma”. Do not use.
Normal detection operation.
Normal detection operation.
Will detect false characters (e.g., those that include “0111”) as “comma”. Do not use.
Similarly, it is recommended not to use differing TXRATE inputs to actual TX rate data reception. The
T[19:0] data bus, TBC and REF clock inputs must be at 125Mb/s rates if TXRATE = 1 and 62.5Mb/s if
TXRATE = 0. It is important to note that the PLL will not lock otherwise.
Along with the 20-bit data input to the serializer, the user will also have to send the appropriate transmit
byte clock signal (TBC)—that is, 125MHz when TXRATE = 1 and 62.5MHz when TXRATE = 0. REF and
TBC should be frequency-locked in all cases and should maintain a certain phase relationship as shown in
Figure 6. The output recovered clocks (RBC/RBCN), the output deserialized data (R[19:0]) and the internal
VCO high-speed clock multiplier will be automatically adjusted by the TXRATE and RXRATE signals.
The baud rate of the data stream to be recovered in the deserializer should be within 200ppm of the REF
frequency. In other words:
F
REF
–
TX
–
F
REF
–
RX
≤ 200ppm
G52162-0, Rev. 2.7
8/28/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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