VSC7146RH 查看數據表（PDF） - Vitesse Semiconductor

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VSC7146RH

2.5Gb/s, 20-Bit Transceiver

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

2.5Gb/s, 20-Bit Transceiver

Advance Product Information

VSC7146

Figure 4: Transmit Timing Waveforms

TBC

T[0:19] Data Valid

20-Bit Data

T1

T2

Data Valid

Data Valid

Table 3: Transmit AC Characteristics

Parameters Description

Min Typ Max Units

Conditions

T1

T[0:19] setup time to the rising

edge of TBC

1.5

T2

T[0:19] hold time after the rising

edge of TBC

1.0

TSDR,TSDF TX+/TX- rise and fall time

—

TLAT

Latency from rising edge of TBC

to T0 appearing on TX+ TX-

Transmitter Output Jitter Allocation

24 bc

+1ns

—

—

160

45 bc

+1ns

Measured between the valid

ns data level of T[0:19] to the

1.4V point of TBC.

ns

ps

Bit

Clock

20% to 80% into 50Ω load to

VSS.

Tested on a sample basis.

Bit clock periods

(PLL locked)

TRJ

Serial data output random jitter

(RMS)

—

5

7.5

ps RMS, tested on a sample basis.

TDJ

Serial data output deterministic

jitter (p-p)

—

25

30

ps

Peak-to-peak, tested on a

sample basis.

Page 6

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G52162-0 Rev. 2.7

8/28/00

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