VSC7146RH 查看數據表（PDF） - Vitesse Semiconductor
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VSC7146RH Datasheet PDF : 19 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7146
2.5Gb/s, 20-Bit Transceiver
Figure 5: Receive Timing Waveforms
RBCN
RBC
R[0:19] and
COM_DET
T3 T3
Data Valid
T1
T2
Data Valid
Data Valid
Table 4: Receive AC Characteristics
Paramete
rs
T1
T2
T3
TR1, TF1
TR2, TF2
RLAT
TRBC
DC
TLOCK
Description
Data or COM_DET valid prior to
RBCN rise
Data or COM_DET valid after
RBCN rise
Time difference between RBC and
RBCN edges
RBC/RBCN rise and fall time
R[0:19], COM_DET rise and fall
time
Latency from RX to R[0:19]
RBC period
RBC duty cycle
Data acquisition lock time @
2.5Gb/s
Min.
1.0
2.0
5.0
10.0
—
0.6
0.7
36bc+
2ns
7.9
15.8
40%
—
Max.
—
—
1
2.0
2.4
56bc+
2ns
8.1
16.2
60%
1250
Units
ns
ns
ns
ns
ns
Bit
Clocks
ns
period
Bit
Clocks
Conditions
Measured between the 1.4V point of
RBCN and a valid level of R[0:19] or
COM_DET. All outputs driving 10pF load.
The spec on top relects RXMODE=1 and
the bottom one reflects RXMODE=0.
Between VIL(max) and VIH(min), into
10pF load.
Between VIL(max) and VIH(min), into
10pF load.
When locked to valid data.
The spec on top relects RXMODE=1 and
the bottom one reflects RXMODE=0.
Tested on a sample basis. 95% probability
of lock.
G52162-0, Rev. 2.7
8/28/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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