VSC7217 查看數據表（PDF） - Vitesse Semiconductor
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VSC7217 Datasheet PDF : 36 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7217
Multi-Gigabit Interconnect Chip
LBENn(1:0)
RXP/Rn
LBTXn
PRXn+
PRXn-
RRXn+
RRXn-
Figure 11: Parallel Loopback Mode Operation
Clk/Data
Recovery
8
10 8B/10B 8 Elastic
Decode 3 Buffer
Rn(7:0)
IDLEn
KCHn
ERRn
PSDETn
RSDETn
≈REFCLK
RECEIVER
(dec)
1
0
Tn(7:0)
8
C/Dn
0
WSENn
≈REFCLK
11
KCHAR
0
PARLOOP
8
DQ
PTXENn
8B/10B 10
Encode
RTXENn
LBTXn
PTXn+
PTXn-
RTXn+
RTXn-
TRANSMITTER
Figure 12: BIST Mode Operation
BIST
Gen 1
Tn(7:0)
C/Dn
WSENn
≈REFCLK
8
0
01
KCHAR
0
BIST
8
DQ
PTXENn
8B/10B 10
Encode
RTXENn
LBENn(1:0)
RXP/Rn
LBTXn
PTXn+ PRXn+
PTXn- PRXn-
RTXn+ RRXn+
RTXn- RRXn-
TRANSMITTER
Clk/Data
Recovery
PSDETn
RSDETn
8
10 8B/10B 8 Elastic
Decode 3 Buffer
WORDCLK
BIST
Chk
RECEIVER
} From Tx
Clock Gen
CGERRn
1
0
BIST
Rn(7:0)
IDLEn
KCHn
ERRn
TBERRn
Built-In Self-Test Operation
Built-In Self-Test operation is enabled when the BIST input is HIGH, which causes TMODE(2:0) to be
internally set to 000. Upon entering BIST mode, the transmitter will issue a Word Sync Sequence in order to
recenter the elasticity buffers in the receive channel. Each transmitter then repeatedly sends a simple 256-byte
incrementing data pattern (prior to 8B/10B encoding) followed by three IDLE characters (K28.5). Note that this
incrementing pattern plus three IDLEs will cause both disparities of each data character and the IDLE character
to be transmitted, and contains a sufficient IDLE density for any application requiring IDLE insertion/deletion.
It is up to the user to enable IDLE insertion/deletion if the receiver’s word clock is not frequency-locked to the
transmitter’s REFCLK.
Each receiver monitors incoming data for this pattern and indicates if any errors are detected. Correct
reception of the pattern is reported on each receiver’s TBERRn output. A LOW means the pattern is being
received correctly and a HIGH means that errors are detected. When BIST transitions from LOW to HIGH,
each TBERRn output is initialized HIGH. It will be cleared LOW whenever one or more IDLE characters, fol-
lowed by all 256 data characters, are sequentially received without error, and set HIGH whenever a pattern mis-
match or receiver error is encountered. Each channel functions independently, no attempt is made to word-align
the receive channels. Received data and associated status will be output as in normal operation. Please note that
Serial Loopback mode and receiver output timing mode selection via RMODE(1:0) operate independently of
BIST mode, but BIST mode disables Parallel Loopback mode.
G52325-0, Rev. 3.0
6/14/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 17
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