VSC8115 查看數據表（PDF） - Vitesse Semiconductor
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VSC8115 Datasheet PDF : 12 Pages
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Target Specification
VSC8115
VITESSE
SEMICONDUCTOR CORPORATION
STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit
Figure 1: Control Diagram for Signal Detection and PLL Bypass Operation
2
DATAIN+/-
PLL Clock
(on-chip)
0
REFCLK
1
STS12
BYPASS
2
DATAOUT+/-
2
CLKOUT+/-±
LOCKREFN
SD
LOS
(on-chip)
Table 1: Signal Detection and PLL Bypass Operation Control
STS12
1
1
1
1
1
0
0
0
0
0
BYPASS
0
0
0
0
1
0
0
0
0
1
LOCKREFN
1
1
0
0
X
1
1
0
0
X
SD LOS DATAOUT CLKOUT
1
0
DATIN
PLL Clock
0
1
LOW
PLL Clock
1
1
LOW
PLL Clock
0
1
LOW
PLL Clock
X
0
DATIN
REFCLK
1
0
DATIN
PLL Clock
0
1
LOW
PLL Clock
1
1
LOW
PLL Clock
0
1
LOW
PLL Clock
X
0
Not Allowed Not Allowed
G52272-0, Rev. 1.1
9/29/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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