VSC8115YA2 查看數據表（PDF） - Vitesse Semiconductor

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VSC8115YA2

STS-12/STS-3 Multi Rate Clock and Data Recovery Unit

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

Target Specification

VSC8115

AC Characteristics

Table 2: Performance Specifications

Parameters

Min Typ Max Units

Conditions

VCO Center Frequency

— 622.08 —

MHz

CRU’s Reference Clock Frequency

Tolerance

-250

—

+250 ppm

OC-12/STS12 Capture Range

—

±500

—

ppm

With respect to the fixed

reference frequency

Clock Output Duty Cycle

45

—

55

% of UI

20% Minimum transition

density

Acquisition Lock Time OC-12/STS-12 —

—

16

µs

Valid REFCLK and device

already powered up

LVDS Output Rise & Fall Times

—

—

600

ps

10% to 90%, with 100Ω & 5pF

capacitive equivalent load

CLKOUT+/- Jitter Generation

—

0.005 0.01

U.I.

No more than 14ps rms jitter on

DATAIN+/-

OC-12/STS-12 Jitter Tolerance

Sinusoidal input jitter of

0.5

—

—

U.I. DATAIN+/- from 250KHz to

5MHz

Page 4

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52272-0, Rev. 1.1

9/29/00

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