VSC8115YA1 查看數據表（PDF） - Vitesse Semiconductor

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VSC8115YA1

STS-12/STS-3 Multi Rate Clock and Data Recovery Unit

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

Target Specification

VSC8115

Retimed Data and Clock Outputs AC Specification

As indicated in figure 3, it is recommended that the retimed data output be captured with the rising edge of

the clock output. Data valid time is larger for OC-3/STS-3 mode of operation than that of OC-12/STS-12. Data

valid time before the output clock’s rising edge is the available setup time (tsu) while the data valid time after

the clock’s rising edge is the available hold time (th).

Figure 3: Retimed Data and Clock Outputs Timing Diagram

DATAOUT+/-

CLKOUT+

tsu

th

Table 3: Retimed Data and Clock Outputs Timing

Parameters

tsu

th

Description

Minimum Available Setup Time

Minimum Available Hold Time

STS-12 Operation

(622.08MHz)

450 pS

650 pS

STS-3 Operation

(155.52MHz)

2.0 nS

3.0 nS

High Speed Outputs

The high speed output buffers, DATAOUT+/- and CLKOUT+/-, can be terminated as either LVDS or

LVPECL outputs. If used as LVDS outputs, the transmission lines should be routed with 100-ohm differential

impedance, and they need to be terminated at the receive end with a 100-ohm resistor across the differential

pair. If used as LVPECL outputs, the transmission line should be 50-ohm terminated with 50-ohm pull down

resistors near the receiving end.

Page 6

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52272-0, Rev. 1.1

9/29/00

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