VSC8115YA 查看數據表（PDF） - Vitesse Semiconductor
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VSC8115YA Datasheet PDF : 12 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Target Specification
VSC8115
STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit
Absolute Maximum Ratings(1)
Power Supply Voltage (VDD) Potential to GND.................................................................................-0.5V to +4V
DC Input Voltage (LVPECL Inputs)..................................................................................... -0.5V to VDD + 0.5V
DC Input Voltage (LVTTL Inputs) ....................................................................................... -0.5V to VDD + 0.5V
Output Current (LVDS or LVPECL Outputs).......................................................................................... +/-50mA
Case Temperature Under Bias.........................................................................................................-55o to +125oC
Storage Temperature .................................................................................................................... -65oC to +150oC
Maximum Input ESD (Human Body Model)
High Speed Outputs (pins 11, 12, 13, & 14) .................................................................................... 500V
All Other Pins ................................................................................................................................. 1500V
Note: Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing
permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
Recommended Operating Conditions
Power Supply Voltage (VDD)................................................................................................................+3.3V ±5 %
Industrial Operating Ambient Temperature Range under Bias ......................................................... -40o to 85oC
Commercial Operating Ambient Temperature Range under Bias ....................................................... 0o to 70oC
Package Pin Descriptions
Figure 4: Pin Diagram
VDDA
DATAIN+
DATAIN-
VSSA
LOCKDET
STS12
REFCLK
LOCKREFN
VSS
VDD
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VDDA
VSSA
CAP+
CAP-
BYPASS
SD
DATAOUT+
DATAOUT-
CLKOUT+
CLKOUT-
G52272-0, Rev. 1.1
9/29/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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