VSC8117QP1 查看數據表（PDF） - Vitesse Semiconductor
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VSC8117QP1
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
Vitesse Semiconductor
VSC8117QP1 Datasheet PDF : 22 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Table 4: Transmit Data Input Timing Table (STS-12 Operation)
Parameter
Description
Min
TCLKOUT Transmit data output byte clock period
-
TINSU
Transmit data setup time with respect to TXLSCKOUT
1.0
TINH
Transmit data hold time with respect to TXLSCKOUT
1.0
Typ
12.86
-
-
Data Sheet
VSC8117
Max
-
-
-
Units
ns
ns
ns
Table 5: Transmit Data Input Timing Table (STS-3 Operation)
Parameter
Description
Min
Typ
TCLKOUT Transmit data output byte clock period
-
51.44
TINSU
Transmit data setup time with respect to TXLSCKOUT
1.0
-
TINH
Transmit data hold time with respect to TXLSCKOUT
1.0
-
Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case
Figure 10: Receive Data Output Timing Diagram
Max
-
-
-
Units
ns
ns
ns
RXCLKIN+
RXCLKIN-
RXLSCKOUT
RXOUT [7:0]
FP
TRXCLKIN
TRXLSCK
TRXVALID
A1
A2
A2
A2
A2
TRXVALID
Table 6: Receive Data Output Timing Table (STS-12 Operation)
Parameter
Description
Min
TRXCLKIN Receive clock period
-
TRXLSCK
Receive data output byte clock period
-
TRXVALID
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
4.0
TPW
Pulse width of frame detection pulse FP
-
Typ
1.608
12.86
-
12.86
Max
-
-
-
-
Units
ns
ns
ns
ns
Page 10
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52221-0, Rev 4.1
1/8/00
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