VSC8117 查看數據表（PDF） - Vitesse Semiconductor

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VSC8117

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Data Sheet

VSC8117

Table 11: Clock Multiplier Unit Performance

Name

RCd

RCj

RCj

RCf

Description

Reference clock duty cycle

Reference clock jitter (RMS) @ 77.76 MHz ref (1)

Reference clock jitter (RMS) @ 19.44 MHz ref (1)

Reference clock frequency tolerance (2)

Min

Typ

Max

Units

40

60

%

13

ps

5

ps

-20

+20

ppm

(1) These Reference Clock Jitter limits are required for the outputs to meet SONET system level jitter requirements

(< 10 mUIrms)

(2) Needed to meet SONET output frequency stability requirements

Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter.

AC Characteristics

Table 12: PECL and TTL Outputs

Parameters

TR,TTL

TF,TTL

TR,PECL

TF,PECL

Description

TTL Output Rise Time

TTL Output Fall Time

PECL Output Rise Time

PECL Output Fall Time

Min Typ Max Units

Conditions

—

2

—

ns 10-90%

—

1.5

—

—

350

—

ns 10-90%

ps 20-80%

—

350

—

ps 20-80%

DC Characteristics

Table 13: PECL and TTL Inputs and Outputs

Parameters

VOH

VOL

VOCM

∆VOUT75

Description

Output HIGH

voltage (PECL)

Output LOW

voltage (PECL)

O/P Common

Mode Range

(PECL)

Differential

Output Voltage

(PECL)

Min

Typ

—

—

0.7

—

1.1

—

600

—

Max

VDDP – 0.9V

—

VDDP – 1.3V

1300

Units

Conditions

V—

V—

V—

mV 75Ω to VDDP – 2.0 V

Page 12

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52221-0, Rev 4.1

1/8/00

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