VSC8117QP2 查看數據表（PDF） - Vitesse Semiconductor

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VSC8117QP2

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

Data Sheet

VSC8117

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Table 13: PECL and TTL Inputs and Outputs

Parameters

∆VOUT50

VIH

VIL

∆VIN

VICM

VOH

VOL

VIH

VIL

IIH

IIL

Description

Differential

Output Voltage

(PECL)

Input HIGH

voltage (PECL)

Input LOW

voltage (PECL)

Differential Input

Voltage (PECL)

I/P Common

Mode Range

(PECL)

Output HIGH

voltage (TTL)

Output LOW

voltage (TTL)

Input HIGH

voltage (TTL)

Input LOW

voltage (TTL)

Input HIGH

current (TTL)

Input LOW

current (TTL)

Min

Typ

Max

Units

Conditions

600

—

1300

mV 50Ω to VDDP – 2.0 V

VDDP – 0.9V —

0

—

400

—

VDDP – 0.3V

VDDP – 1.72V

1600

V For single ended

V For single ended

mV —

1.5 – ∆VIN/2 — VDDP – 1.0 – ∆VIN/2

V

—

2.4

—

—

—

—

0.5

2.0

—

5.5

0

—

0.8

—

50

500

—

—

-500

V IOH = -1.0 mA

V IOL = +1.0 mA

V—

V—

µA

2.0V< VIN < 5.5V,

Typical@2.4V

µA -0.5V < VIN < 0.8V

Power Dissipation

Table 14: Power Supply Currents

Parameter

IDD

PD

Description

Power supply current from VDD

Power dissipation (worst case)

(Max)

480

1.6

Units

mA

W

G52221-0, Rev. 4.1

1/8/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 13

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