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VSC8117QP2 查看數據表(PDF) - Vitesse Semiconductor

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VSC8117QP2 Datasheet PDF : 22 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Data Sheet
VSC8117
Table 15: Pin Identification
Signal
Pin
I/O
LOSPECL
33
I
VDD
34
VSS
35
REFCLK
36
I
VSSA
37
VDDA
38
CP1
39
CN1
40
CN2
41
CP2
42
VDDA
43
VSSA
44
VSS
45
VSS
46
VDD
47
VDD
48
TXLSCKOUT
49
O
TXIN7
50
I
TXIN6
51
I
VSS
52
TXIN5
53
I
TXIN4
54
I
TXIN3
55
I
TXIN2
56
I
TXIN1
57
I
TXIN0
58
I
STS12
59
I
CRUREFSEL
60
I
VDD
61
EQULOOP
62
I
FACLOOP
CRUEQLP
63
I
64
I
Level
PECL
+3.3V
GND
TTL
GND
+3.3V
Analog
Analog
Analog
Analog
+3.3V
GND
GND
GND
+3.3V
+3.3V
TTL
TTL
TTL
GND
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
+3.3V
TTL
TTL
TTL
Pin Description
Loss of Signal Control- Single ended PECL input; active low
+3.3V Power Supply
Ground
Reference clock input, refer to table 10
Analog Ground (CMU)
Analog Power Supply (CMU)
CMU external capacitor (see Figure 6, and Table 1)
CMU external capacitor (see Figure 6, and Table 1)
CMU external capacitor (see Figure 6, and Table 1)
CMU external capacitor (see Figure 6, and Table 1)
Analog Power Supply (CRU)
Analog Ground (CRU)
Ground
Ground
+3.3V Power Supply
+3.3V Power Supply
Transmit byte clock out
Transmit input data bit7
Transmit input data bit6
Ground
Transmit input data bit5
Transmit input data bit4
Transmit input data bit3
Transmit input data bit2
Transmit input data bit1
Transmit input data bit0
155Mb/s or 622Mb/s mode select, refer to table 10
Selects between CMU’s or CRU’s REFCLK
+3.3V Power Supply
Equipment loopback, loops low speed byte wide transmit
input data to receive output bus
Facility loopback, loops high speed receive data and clock
directly to transmit outputs.
Loops TXDATAOUT to the CRU replacing RXDATAIN+/-
Page 16
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52221-0, Rev 4.1
1/8/00

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