VSC8117QP1 查看數據表（PDF） - Vitesse Semiconductor

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VSC8117QP1

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Data Sheet

VSC8117

CRU clock and data signals. (In this mode the VSC8117 operates just like the VSC8111 and VSC8116). The

receive section also contains a SONET/SDH frame detector circuit which is used to provide frame pluses during

the A1, A2 boundary in the serial to parallel converter. This only occurs when OOF is high. Both internal and

external LOS functions are supported. The high speed serial signals can be made PECL compatible or LVPECL

compatible by setting the proper voltage on the VDDP supply pins

VSC8117 Block Diagram

EQULOOP

DSBLCRU

RXDATAIN+/-

CRUEQLP

RXCLKIN+/-

1

1

0

0

REC-DATA

CRU

0

REC-CLK

1

CRUREFCLK

CRUREFSEL

losdet

0

1

TXDATAOUT+/-

FACLOOP

1

QD

0

1

0

DQ

0

1

FRAMER

OOF

FP

0

1

1:8

DEMUX

8

DQ

RXOUT[7:0]

0

Divide-by-8

1

RXLSCKOUT

LOSPECL

LOSDETEN_

1

0

CMU

STS12

REFCLKP+/-

REFCLK

CMUFREQSEL

LOOPTIM0

8:1

MUX

8

QD

TXIN[7:0]

Divide-by-8

TXLSCKOUT

Page 2

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52221-0, Rev 4.1

1/8/00

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