VSC8117 查看數據表（PDF） - Vitesse Semiconductor

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VSC8117

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

Data Sheet

VSC8117

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Figure 3: Facility Loopback Data Path

RXDATAIN

RXCLKIN

TXDATAOUT

FACLOOP

CRU

DQ

Recovered

Clock

0

1

1

QD

0

1

0

1:8

Serial to

Parallel

DQ

Divide-by-8

8:1

Parallel to

Serial

QD

PLL

RXOUT[7:0]

RXLSCKOUT

TXIN[7:0]

Equipment Loopback

The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is

set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the paral-

lel to serial conversion of the low speed data (TXIN[7:0]) is selected and converted back to parallel data in the

receiver section and presented to the low speed parallel outputs (RXOUT[7:0]). See Figure 4. The internally

generated 155/622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In Equip-

ment Loopback mode the transmit data (TXIN[7:0]) is serialized by the on-chip CMU and presented at the high

speed output (TXDATAOUT).

CRU Equipment Loopback

Exactly the same as equipment loopback, the point where the transmit data is looped back is moved all the

way back to the high speed I/O. When the CRUEQLP signal is set high, transmit data is looped back to the

CRU, replacing RXDATAIN±

Figure 4: Equipment Loopback Data Path

RXDATAIN

EQULOOP

TXDATAOUT

DQ

0

1

QD

1:8

Serial to

Parallel

÷8

8:1

Parallel to

Serial

DQ

QD

PLL

÷8

RXOUT[7:0]

RXLSCKOUT

TXIN[7:0]

TXLSCKOUT

G52221-0, Rev. 4.1

1/8/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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