VSC8117QP1 查看數據表（PDF） - Vitesse Semiconductor

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VSC8117QP1

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Data Sheet

VSC8117

Split Loopback

Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data

received (RXDATAIN) is mux’d through to the high-speed serial output (TXDATAOUT). The low-speed trans-

mit byte wide bus(TXIN[7:0]) and (TXLSCKIN) are mux’d into the low-speed byte wide receive output bus

(RXOUT[7:0]) and (RXLSCKOUT). See Figure 5.

Figure 5: Split Loopback Datapath

RXDATAIN

RXCLKIN

DSBLCRU

TXDATAOUT

CRU

DQ

Recovered

Clock

0

1

QD

1:8

Serial to

Parallel

8:1

Parallel to

Serial

PLL

÷8

DQ

QD

TXLSCKIN

RXOUT[7:0]

RXLSCKOUT

TXIN[7:0]

Loop Timing

LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU

is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single

external source.

Clock Synthesis

The VSC8117 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed

clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector

(PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feed-

back system. The PFD compares the selected divided down version of the 622MHz VCO (pin CMUFREQSEL

selects the divide-by ratios of 8 or 32, see Table 10) and the reference clock. The integrator provides a transfer

function between input phase error and output voltage control. The VCO portion of the PLL is a voltage con-

trolled ring-oscillator with a center frequency of 622MHz.

The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the

amplifier through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface mounted

capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable

reference frequencies.

Page 6

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52221-0, Rev 4.1

1/8/00

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