VSC8117QP1 查看數據表（PDF） - Vitesse Semiconductor

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VSC8117QP1

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

Data Sheet

VSC8117

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

AC Timing Characteristics

RXCLKIN+

RXCLKIN-

RXDATAIN+

RXDATAIN-

Figure 8: Receive High Speed Data Input Timing Diagram

TRXCLK

TRXSU

TRXH

Table 2: Receive High Speed Data Input Timing Table (STS-12 Operation)

Parameter

TRXCLK

TRXSU

TRXH

Description

Receive clock period

Serial data setup time with respect to RXCLKIN

Serial data hold time with respect to RXCLKIN

Min

Typ

-

1.608

400

-

100

-

Max

-

-

-

Units

ns

ps

ps

Table 3: Receive High Speed Data Input Timing Table (STS-3 Operation)

Parameter

TRXCLK

TRXSU

TRXH

Description

Receive clock period

Serial data setup time with respect to RXCLKIN

Serial data hold time with respect to RXCLKIN

Min

Typ

-

6.43

1.5

-

1.5

-

Figure 9: Transmit Data Input Timing Diagram

TXLSCKOUT

TXIN [7:0]

TCLKOUT

TINSU

TINH

Max

-

-

-

Units

ns

ns

ns

G52221-0, Rev. 4.1

1/8/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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