VSC838UG 查看數據表（PDF） - Vitesse Semiconductor
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VSC838UG Datasheet PDF : 20 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC838
I/O Equivalent Circuits
ITC
VCC
50
PAD
50
50
PAD PAD
3.2Gb/s
36x37 Crosspoint Switch
TERM_CTRL
50
PAD
H/S Input Equivalent Circuit
DRIVE_CTRL
H/S Output Equivalent Circuit
Input Termination
The high-speed inputs of the VSC838 are internally terminated by a 100Ω impedance between true and
complement inputs. Termination resistors are isolated from each other on-chip. The termination will self-bias to
+2.0V (nominal) for AC-coupled applications. The ITC pin enables direct interconnection of multiple VSC838
devices. With ITC tied to VCC, the center point of the 100Ω termination impedance is tied to VCC, causing the
terminations to act as loads for an open-drain or open-collector differential output.
Table 7: Allowed Input Termination Schemes
Type Description
1 AC-coupled input
2 DC-coupled from open-drain CML
3 DC-coupled from back-terminated 2.5V CML
4 DC-coupled from back-terminated 2.5V CML
5 DC-coupled from back-terminated 3.3V LV-PECL
Comments
Tie ITC LOW, 100Ω differential input termination,
input self-biased
Tie ITC HIGH, terminations acts as 50Ω load to VCC
Tie ITC HIGH, terminations acts as 50Ω load to VCC
Tie ITC LOW, 100Ω differential termination
(preferred over Type 3)
Tie ITC LOW, 100Ω differential termination
Some allowed termination schemes result in additional ICC current and power dissipation on-chip. See
Table 8.
Table 8: Additional Current and Power
Parameter
Description
Min Typ Max Units
ICC-C
PCC-C
Additional ICC current when receiving DC-
Coupled CML (ITC = HIGH)
Additional power dissipated on-chip for
DC terminating CML at inputs
180
mA
0.180
W
Conditions
G52351-0, Rev 3.0
02/12/01
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