VSC870TX 查看數據表（PDF） - Vitesse Semiconductor
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VSC870TX Datasheet PDF : 40 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC870
High Performance Serial
Backplane Transceiver
Package Pin Descriptions
Symbol
TXIN[31:0]
TXTYP[1:0]
TXEN
RTR
RTM/TCLK
RFM
TXOK
REN
MODE[1:0]
TXSA+/
TXSA-
TXSB+/
TXSB-
LOOPBACK
RXSA+/
RXSA-
RXSB+/
RXSB-
Name
I/O
Transmit Parallel Data In I
Transmit Word Type
I
Transmit Enable
I
Ready To Receive
I
Retransmit Mode/
Transmit Cell Clock
O
Read From Mark
O
Transmit signal OK
O
Read Enable
O
Mode Control
I
Transmit Serial Output A O
Transmit Serial Output B O
Loop Back
I
Receive Serial Input A I
Receive Serial Input B I
Freq
Type
62.5Mb/s
TTL
62.5Mb/s
TTL
62.5Mb/s
TTL
62.5Mb/s
TTL
62.5Mb/s
TTL
62.5Mb/s
TTL
<1MHz
TTL
62.5Mb/s
TTL
<1MHz
TTL
2.125Gb/s
LVDS
2.125Gb/s
LVDS
<1MHz
TTL
2.125Gb/s
LVDS
2.125Gb/s
LVDS
Description
32-bit parallel data input for the transmit side.
If BYPASS is LOW, these signals designate the transmit
word type. If BYPASS is HIGH, these signals directly
control the overhead bits sent on the serial channel.
When TXEN is HIGH, TXIN[31:0], TXTYP[1:0] are
loaded in to the transceiver on the next WCLK. When
TXEN is LOW, the transceiver ignores TXIN[31:0] and
TXTYP[1:0] and sends IDLE words at the serial output.
When RTR is HIGH, the receiving side memory system is
ready to receive data. If LOW, it sends a back pressure
(flow control) signal to the source port card telling it to
stop sending data. In Cell Mode, set RTR LOW to cell
synchronize to the external cell clock. If RTR is HIGH,
cell clock is recovered from the bit stream.
In Packet Mode, when BYPASS is LOW, RTM/TCLK is
set HIGH at the beginning of each data transmission and
set LOW when the data packet has been successfully sent
to all outputs. In Cell Mode, a HIGH pulse represents the
transmit cell clock.
When BYPASS is LOW, RFM is set HIGH whenever a
retransmission of data is required due to contention for
destination ports.
This signal is LOW if MODE[1] is HIGH and the
transceiver is word aligned on the transmit side. After
initialization it will go HIGH for one word clock if there
is a cell clock error.
When REN is HIGH, the transceiver is ready to read data
at TXIN[31:0] and TXTYP[1:0]. This signal can be
forced low by the received flow control signal.
These mode control pins are used to configure link
synchronization. See Section 1.5.
High speed serial differential transmit channel A
High speed serial differential transmit channel B
When LOOPBACK is HIGH, the CRU and signal
detector select the serial data output channel as an input.
High speed serial differential receive channel A
High speed serial differential receive channel B
G52190-0, Rev 4.1
01/05/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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