VSC8022FI 查看數據表（PDF） - Vitesse Semiconductor

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VSC8022FI

8-Bit MUX/DEMUX Chipset 2.5Gb/s SONET-Compatible

Vitesse Semiconductor 

(1)

CLKI (CLKIN)

High speed differential clock input

OOFN

Frame recovery clock input

DI (DIN)

High speed serial data inputs

tC

t OOFNPW

t OOFN

A1

A1

BYCKO (BYCKON)

Byte clock output

D1 (D1N)

BYCKO Resynch

D2 (D2N)

D3 (D3N)

D4 (D4N)

D5 (D5N)

D6 (D6N)

D7 (D7N)

D8 (D8N)

Parallel Data• (2)

Output Summary

FP

Frame detection confirm output

SONET STS-3 Framing Sequence

DATA

DATA

DATA DATA

DATA

A1

A2

A2

A2

tD

t BD

Valid

Data

Valid

Valid

Data Valid

Valid

Data Valid

Data

Data

Data

Valid

Data Valid

Data

Valid

Data Valid

Data

Valid

Data Valid

Data

Valid

Data Valid

Data

Valid

Data Valid

Data

A1

A1

A2

A2

A2 Data Data Data Data

t DFP

t PFP

NOTES:

1) Negative edge is active edge.

2) The parallel data outputs only begin showing valid data after the last A2 of the SONET framing sequence. The example

waveforms shown above use an STS-3 framing sequence for convenience, thus valid data is output after the third

A2 in the sequence.

= Don’t care.

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