VSC8061QH 查看數據表（PDF） - Vitesse Semiconductor
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VSC8061QH Datasheet PDF : 20 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8061/VSC8062
2.5Gb/s 16-Bit
Multiplexer/Demultiplexer Chipset
VSC8062 Demultiplexer AC Characteristics (Over recommended operating range)
Figure 6: VSC8062 Timing Diagram
CLK (CLKN)
tCLK
High-speed differential clock input
DI (DIN)
High-speed serial data input
CLK16
Parallel data clock output
D0
tD
tBD
tD
D1
D15
Table 2: VSC8062 AC Characteristics
Parameter
tCLK
tD
tDSU
tDH
Description
Clock period(1)
BYTE CLK16 period (tCLK x 16)
CLK16 falling edge output to valid data
Phase
Margin
=
1
–
t--S---tU--C---+L---K--t--H--
×
360°
Serial data phase timing margin with respect to
high-speed clock(2)
Min Typ Max Units
400
ps
6.4
ns
1.0
3.0
ns
Conditions
180(3)
degrees
NOTES: (1) If tCLK changes, all remaining parameters change as indicated by the equations.
(2) tSU and tH are setup and hold times of the serial data input register.
(3) At tCLK = 400ps.
G52069-0, Rev 4.3
05/11/01
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