VSC837UG 查看數據表（PDF） - Vitesse Semiconductor
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VSC837UG Datasheet PDF : 26 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
3.2Gb/s
68x68 Crosspoint Switch
Preliminary Data Sheet
VSC837
Functional Block Diagram
A, AN[0:67]
CONFIG
INITB
68x69 Switch Core
Core Program Registers
Program Memory
Program Interface
Y, YN[0:67]
Internal 69th Output
Activity
Monitor
Functional Description
Input / Output Characteristics
All input data must be differential and should be nominally biased to +2.0V or AC-coupled. Other levels
are allowed as described under the Input Termination section. On-chip terminations are provided, with a nomi-
nal impedance of 100Ω differential. All input termination resistors float with an internal bias provided for AC-
coupling.
For direct interconnection of multiple VSC837 devices, a CML termination mode is provided by tying the
ITC pin to VCC, which ties the center point of the 100Ω termination to VCC, causing the terminations to act as
loads for an open-drain or open-collector differential output.
Data outputs are provided through differential current switches with on-chip back-termination. The output
circuit is capable of driving external 50Ω far-end termination (recommended). The output back-terminations are
electronically switchable to enable a power savings of 2W (max) by reducing the output driver current.
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© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52309-0, Rev 3.0
02/16/01
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